1. Field of the Invention
The disclosure relates generally to processing of semiconductor devices and, more specifically, to a method of laser annealing sub-surface features in a semiconductor device.
2. Description of the Related Art
To fulfill the ever-increasing demand for computing power, semiconductor chip manufacturers have approached the task of providing more computing power with a single device using various approaches. One of the most commonly used approaches has been to reduce the size of the features in the semiconductor device, which provides the advantages of higher speed, lower power consumption, and a higher density of semiconductor features (e.g., transistors). However, the ability of manufactures to reduce feature size is becoming more expensive and more difficult and beginning to run into fundamental physical limitations.
As a result of these difficulties, many manufacturers are also employing techniques whereby multiple chips (i.e., multiple modules) are being integrated together to operate as a single chip. Initially, these multiple chips were positioned side-by-side with one another. However, in certain applications, particularly with applications where the available footprint is small (e.g., personal digital assistants and mobile phones), there was a need to vertically stack the chips. The vertical stacking of the chips has the advantage of increased transistor density per a given footprint and increased signal communication speed as the distance between the chips is decreased.
The vertical stacking of multiple chips is commonly referred to as 3-D integration. One technique in fabricating 3-D integrated circuits involves separately fabricating 2-D dies then bonding these separate 2-D dies together. The separate 2-D dies are then connected with inter-die vias that extend through the insulation layers surrounding the dies. An issue associated with this technique regards the need to maintain a proper alignment between the separate dies. Also, the distance between the active layers of the separate 2-D dies may still be a substantial distance apart.
Another technique also involves bonding two separate 2-D dies together. However, in this technique, the respectively active layers of the separate 2-D dies are bonded facing one another. In this manner, a reduced distance between the active layers of the separate 2-D dies may be achieved. However, the alignment issue remains. Moreover, non-standard connections (e.g., deep vias) are needed to connect the die to the interconnectors of the semiconductor package. Another issue associated with this technique is that this technique is only directly extendable to two dies, whereas the previously discussed technique may be directly extendable to greater than two dies. There is, therefore, a need for an improved technique for manufacturing a single die having multiple layers of active devices.